The present invention relates to a semiconductor device.
A technique is known in which a dummy interconnect that is not connected to other interconnects is formed in a semiconductor device having multi-layer interconnects.
For example, Japanese Unexamined Patent Publication No. 2000-223492 discloses a structure in which dummy trench interconnects are arranged in a space around an interconnect isolation portion at the same pitch as that of a portion in which interconnects are densely arranged. In this way, it is possible to remove the difference of the interconnect density and it is possible to uniformly form the trench interconnects with the same dimensions as those of the mask. In addition, when interconnect metal is polished, it is possible to remove the difference between the heights of the interconnects due to the non-uniformity of the density of the interconnects.
Japanese Unexamined Patent Publication No. 03-180041 discloses a structure in which dummy interconnect layers that are not connected to other interconnect layers are arranged on an element isolation region of a peripheral circuit portion at the minimum pitch of the design rule. Therefore, a loading effect is less likely to occur, the dimensions of the interconnect layer do not vary depending on positions, and the characteristics of a transistor do not vary depending on positions.
Japanese Unexamined Patent Publication No. 06-333928 discloses a structure in which a dummy interconnect layer is provided and the amount of resist, which is a deposit supply source, is maintained to be equal to or more than a predetermined value during dry etching, which makes it possible to reduce a variation in the width of a line and a variation in the cross-sectional shape of the line in an LSI chip. In addition, the dummy interconnect layer is arranged at the position where the density of the pattern is low. In this way, it is possible to recover the flatness that has been lost due to the difference of the pattern density.
WO 2006/061871 discloses a structure in which a dummy metal plate with a high aspect ratio is provided in the same layer as that in which interconnects are formed to reduce thermal resistance without increasing the relative permittivity of an insulating layer, which makes it easy to move heat generated from the interconnect. In this way, it is possible to prevent an increase in temperature during the operation of a semiconductor device.
Japanese Unexamined Patent Publication No. 2001-217248 discloses a structure in which, when the density of the trench interconnects provided in an insulating film on a semiconductor substrate is not uniform, a dummy trench is provided in a region of the insulating film in which the density of the interconnects is low, thereby reducing dishing during a CMP process of the insulating film in the region in which the density of the interconnects low.
Japanese Unexamined Patent Publication No. 2005-310902 discloses a SiC power device in which some of a plurality of interconnects are connected to other interconnects by copper plugs.
ISPSD 2009 (21st International Symposium on Power Semiconductor Devices and ICs) p. 77-79 discloses the cross-sectional structure of an N-channel LDMOS. The structure of the LDMOS will be described in brief with reference to FIG. 7. A deep N-type well region which is called a DNW 902 and is formed by 2-MeV phosphor implantation is provided on a P-type silicon substrate 901. A body region, which is called a PW 906, of the LDMOS and a drain region including a drift 907 and an NW 908 are formed on the DNW 902. A gate electrode 903 is formed on the surface of the P-type silicon substrate 901. A drain interconnect 904 and a source interconnect 905 are formed on a silicon oxide film through contact plugs.